Semiconductor memories generally include an orthogonal array of memory cells for storing binary data in the form of ones and zeros. In static RAMS, usually each memory cell includes four or six transistors arranged in a cross-coupled flip-flop coupled to a pair of bit lines and a word line. The array typically includes columns of bit lines and rows of word lines. Customarily, the bit lines are grouped in pairs. A memory cell is located at each intersection of a bit line pair and a word line. A pair of bit lines can be selectively coupled to data lines under the control of one of a number of column select lines which originate from a column address decoder. Each of the word lines which originate from a row address decoder can selectively couple the memory cells in that row to their corresponding bit lines by turning on access transistors in the memory cell. Input addresses are decoded by the column address decoders and row address decoders to couple a particular memory cell, i.e., the memory cell located at the intersection of the selected bit lines and word lines, to the data lines. In this manner, binary data stored in the memory cells may be transferred to the bit lines and then to the data lines for eventual transfer to a memory output device Data is written into the memory cells in the same general manner. A good description of illustrative static RAM circuitry is provided in U.S. Pat. No. 4,355,377 owned by Inmos Corporation and entitled "Asynchronously Equilibrated And Pre-Charged Static RAM," the disclosure of which is incorporated hereby.
The data signal that is read out of a memory cell, whether of the type described supra or not, via the bit lines requires amplification before it can be used to drive the memory output device. This amplification is usually achieved in a number of stages, and the amplifiers used for this purpose are called sense amplifiers. Conventional sense amplifiers have sensed a voltage differential between the bit lines. The voltage difference typically developed between bit lines is on the order of 5% to 10% of the device supply voltage. Thus, for a 5 volt supply, the bit line voltage differential is in the 0.25 to 0.5 volt range.
One problem with sensing the voltage differential between the bit lines is that the bit lines and data lines are capacitively loaded. Accordingly, the generation of the required voltage differential involves a time delay. The time delay caused by the capacitance necessarily increases the time required to read data from a memory cell.
Another problem associated with existing voltage sensing techniques is that the voltage differential remaining on the bit line from a prior operation (reading or writing) may have to be reversed for the correct operation. For example, if one bit line is 0.5 volts below its companion bit line after data has been read from a first memory cell, the bit lines, upon reading the data from a second memory cell, may have to change so the first bit line is now 0.5 volts above its companion bit line. In order to increase the operating speed of the memory circuit, techniques have been developed to "equilibrate" or short together the bit lines so that the voltage differential remaining on the bits from a prior operation is eliminated. For example, U.S. Pat. No. 4,355,377 describes address transition detection circuitry coupled to a clock generator driving precharge and equilibration circuits. One disadvantage of these techniques is that the circuit is very sensitive to the timing of the signals used to control the equilibrating operation.
Further disadvantages of using sensing techniques which depend on the voltage differential between the bit lines are the difficulty in obtaining optimal signal gain from the sense amplifiers and in shifting the common mode voltage level on the bit lines before the differential signal can be used as a memory output signal. Both of these problems are caused by the fact that the bit lines must be maintained above a voltage equal to about 80% of the device supply voltage to preserve memory cell stability.
It is therefore an object of the present invention to provide sense amplifiers for a memory device in which the operating speed of the device is not adversely affected by the capacitance associated with the bit lines.
Another object of the invention is to provide a bit line equalization technique which does not depend upon critical timing signals.
It is a further object of the invention to provide sense amplifiers which have high gain and which simplify the task of level shifting the bit line differential signal to provide an output signal.